FIG. 1 shows a cross-section of a conventional floating body DRAM (dynamic random access memory) memory cell. The conventional floating body DRAM cell is formed in a silicon-on-insulator (SOI) substrate comprising a thin film of silicon 3 separated from the base substrate 1 by a buried oxide layer (BOX) 2. A floating body 4, a source region 5 and a drain region 6 are formed in the thin film 3 on top of the BOX 2. A gate dielectric layer 7 and a gate electrode 8 are sequentially deposited on top of the floating body 4. The drain region 6 is connected to a bit line BL, the source region 5 is connected to a source line SL and the gate electrode 8 is connected to a word line WL.
The floating body is electrically insulated by the BOX, the gate dielectric layer, the source region and the drain region. Because of this insulation, the floating body can store an electrical charge. In a data write operation in such a transistor, the floating body uses an impact ionization phenomenon to store charges, which modifies the threshold voltage of the transistor. In a data read operation, the quantity of the current flowing between the source and the drain of the transistor thus depends on the quantity of charges stored in the floating body.
In order to be able to perform a logic 1 state write operation (operation hereinafter called “write 1”), a relatively high voltage, of around 2.5 times the nominal power supply voltage VDD that has to be applied to the gate electrode, must be applied to the bit line BL. Besides the fact that this high voltage is likely to damage the cell, it can also disrupt the operation of nearby memory cells. The generation of this high voltage also requires dedicated circuitry implementing charge pumps.
One technique for reducing the surface area occupied by such a floating body DRAM memory cell is described in the document US 2004/0108532. This document proposes creating a memory cell by associating a floating body horizontal FET transistor and a horizontal bipolar transistor suitable for injecting charges into the floating body. The low storage capacity of the floating body is thus increased. The horizontal bipolar transistor is more specifically arranged laterally to the FET transistor with the emitter (serving as injector) of the bipolar transistor formed in the substrate with a conductivity opposite to the latter, the base of the bipolar transistor being formed by the substrate and the collector of the bipolar transistor serving as floating body for the FET transistor.
With such an arrangement, the surface area of the memory cell is reduced to approximately 10F2. However, in this arrangement, the emitter and the base consume surface area so that an even greater reduction of the memory cell surface area remains an objective to those skilled in the art.
Moreover, this memory cell has the drawback that it is difficult to accurately control the voltage of the substrate serving as base for the bipolar transistor. Since the injector is, moreover, shared between two adjacent memory cells, the result is a risk of disturbances between these neighbouring cells.
It will therefore be understood that the memory cell according to the document US 2004/0108532 is not totally satisfactory, and that there is still a need to remedy the abovementioned drawbacks in the prior art.